Freescale Semiconductor, Inc.
1. POR or RESET pin
2. Clock monitor reset
3. COP watchdog reset
4. XIRQ interrupt
5. Illegal opcode interrupt
6. Software interrupt (SWI)
The maskable interrupt sources have the following priority arrangement:
1. IRQ
2. Real-time interrupt
3. Timer input capture 1
4. Timer input capture 2
5. Timer input capture 3
6. Timer output compare 1
7. Timer output compare 2
8. Timer output compare 3
9. Timer output compare 4
10.Timer input capture 4/output compare 5
11.Timer overflow
12.Pulse accumulator overflow
13.Pulse accumulator input edge
14.SPI transfer complete
15.SCI system (refer to Figure 5-5)
Any one of these interrupts can be assigned the highest maskable interrupt priority by
writing the appropriate value to the PSEL bits in the HPRIO register. Otherwise, the
priority arrangement remains the same. An interrupt that is assigned highest priority is
still subject to global masking by the I bit in the CCR, or by any associated local bits.
Interrupt vectors are not affected by priority assignment. To avoid race conditions, HP-
RIO can only be written while I-bit interrupts are inhibited.
5.3.1 Highest Priority Interrupt and Miscellaneous Register
HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous
$103C
Bit 7
6
5
4
IRV
0
3
2
1
Bit 0
RBOOT* SMOD*
MDA*
PSEL3
PSEL2
PSEL1
PSEL0
RESET:
0
0
1
0
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Single Chip
Expanded
Bootstrap
1
0
1
Special Test
*The values of the RBOOT, SMOD, MDA, and IRV reset bits depend on the operating mode selected during power-
up. Refer to Table 4–3.
RBOOT — Read Bootstrap ROM
Set to one out of reset in bootstrap mode. Valid while in special modes only. Can be
read any time. Can only be written in special modes. Refer to SECTION 4 OPERAT-
ING MODES AND ON-CHIP MEMORY for more information.
RESETS AND INTERRUPTS
TECHNICAL DATA
5-7
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