Freescale Semiconductor, Inc.
CR[1:0] — COP Timer Rate Select
15
The internal E clock is first divided by 2 before it enters the COP watchdog system.
These control bits determine a scaling factor for the watchdog timer. Refer to Table 5-
1.
5.1.6 CONFIG Register
CONFIG — System Configuration Register
$103F
Bit 7
EE3
1
6
EE2
1
5
EE1
1
4
EE0
1
3
—
1
2
NOCOP
P
1
—
1
Bit 0
EEON
RESET:
1
1
P
0
Single Chip
Bootstrap
1
1
1
1
1
P(L)
P
1
P
P
P
P
1
1
Expanded
Special Test
P
P
P
P
1
P(L)
1
P indicates a previously programmed bit. P(L) indicates that the bit resets to the logic
level held in the latch prior to reset, but the function of COP is controlled by DISR in
TEST1 register.
EE[3:0] — EEPROM Mapping Control
Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY.
Bit 3 — Not implemented
Always reads one
NOCOP — COP System Disable
0 = COP system enabled (forces reset on time-out)
1 = COP system disabled
Bit 1 — Not implemented
Always reads one
EEON — EEPROM Enable
Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY.
5.2 Effects of Reset
When a reset condition is recognized, the internal registers and control bits are forced
to an initial state. Depending on the cause of the reset and the operating mode, the
reset vector can be fetched from any of six possible locations. Refer to Table 5-2.
Table 5-2 Reset Cause, Operating Mode, and Reset Vector
Cause of Reset
POR or RESET Pin
Normal Mode Vector
$FFFE, FFFF
Special Test or Bootstrap
$BFFE, $BFFF
Clock Monitor Failure
$FFFC, FFFD
$BFFC, $BFFD
COP Watchdog Time-out
$FFFA, FFFB
$BFFA, $BFFB
These initial states then control on-chip peripheral systems to force them to known
start-up states, as follows:
RESETS AND INTERRUPTS
MC68HC11F1
5-4
TECHNICAL DATA
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