Freescale Semiconductor, Inc.
Table 9-3 Timer Prescaler Selection
PR[1:0]
0 0
Prescaler
1
4
0 1
1 0
8
1 1
16
NOTE
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in
TMSK2 enable the corresponding interrupt sources.
9.3.10 Timer Interrupt Flag Register 2
Bits in this register indicate when certain timer system events have occurred. Coupled
with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to
operate in either a polled or interrupt driven system. Each bit of TFLG2 corresponds
to a bit in TMSK2 in the same position.
TFLG2 — Timer Interrupt Flag 2
$1025
Bit 7
TOF
0
6
RTIF
0
5
PAOVF
0
4
PAIF
0
3
—
0
2
—
0
1
—
0
Bit 0
—
RESET:
0
Clear flags by writing a one to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time (Periodic) Interrupt Flag
Refer to 9.4 Real-Time Interrupt.
PAOVF — Pulse Accumulator Overflow Interrupt Flag
Refer to 9.6 Pulse Accumulator.
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Refer to 9.6 Pulse Accumulator.
Bits [3:0] — Not implemented
Always read zero
9.4 Real-Time Interrupt
The real-time interrupt (RTI) feature, used to generate hardware interrupts at a fixed
periodic rate, is controlled and configured by two bits (RTR1 and RTR0) in the pulse
accumulator control (PACTL) register. The RTII bit in the TMSK2 register enables the
interrupt capability. The four different rates available are a product of the MCU oscil-
lator frequency and the value of bits RTR[1:0]. Refer to Table 9-4, which shows the
periodic real-time interrupt rates.
TIMING SYSTEM
MC68HC11F1
9-12
TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
