Timer Module (TIM16B8CV2) Block Description
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0006
TSCR1
R
0
0
0
TEN
TSWAI
TSFRZ
TFFCA
PRNT
W
0x0007
TTOV
R
TOV7
OM7
OM3
EDG7B
EDG3B
C7I
TOV6
OL7
TOV5
OM6
TOV4
OL6
TOV3
OM5
TOV2
OL5
TOV1
OM4
TOV0
OL4
W
0x0008
TCTL1
R
W
0x0009
TCTL2
R
OL3
OM2
OL2
OM1
OL1
OM0
OL0
W
0x000A
TCTL3
R
EDG7A
EDG3A
EDG6B
EDG2B
EDG6A
EDG2A
EDG5B
EDG1B
C3I
EDG5A
EDG1A
C2I
EDG4B
EDG0B
C1I
EDG4A
EDG0A
C0I
W
0x000B
TCTL4
R
W
0x000C
TIE
R
C6I
0
C5I
0
C4I
0
W
0x000D
TSCR2
R
TOI
TCRE
PR2
PR1
PR0
W
0x000E
TFLG1
R
C7F
C6F
0
C5F
0
C4F
0
C3F
0
C2F
0
C1F
0
C0F
0
W
0x000F
TFLG2
R
TOF
W
R
Bit 15
Bit 14
Bit 6
Bit 13
Bit 5
Bit 12
Bit 4
Bit 11
Bit 3
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
W
0x0010–0x001F
TCxH–TCxL
R
Bit 7
0
W
0x0020
PACTL
R
PAEN
0
PAMOD
0
PEDGE
0
CLK1
0
CLK0
0
PAOVI
PAOVF
PAI
W
0x0021
PAFLG
R
0
PAIF
W
0x0022
PACNTH
R
PACNT15 PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 PACNT9
PACNT8
PACNT0
W
0x0023
PACNTL
R
PACNT7
PACNT6
PACNT5
PACNT4
PACNT3
PACNT2
PACNT1
W
0x0024–0x002B
Reserved
R
W
= Unimplemented or Reserved
Figure 14-5. TIM16B8CV2 Register Summary (Sheet 2 of 3)
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
479
FREESCALE [ Freescale ]
