Timer Module (TIM16B8CV2) Block Description
14.3.2.4 Output Compare 7 Data Register (OC7D)
Module Base + 0x0003
7
6
5
4
3
2
1
0
R
W
OC7D7
OC7D6
OC7D5
OC7D4
OC7D3
OC7D2
OC7D1
OC7D0
Reset
0
0
0
0
0
0
0
0
Figure 14-9. Output Compare 7 Data Register (OC7D)
Read: Anytime
Write: Anytime
Table 14-5. OC7D Field Descriptions
Description
Field
7:0
Output Compare 7 Data — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a
OC7D[7:0] successful output compare on channel 7, can cause bits in the output compare 7 data register to transfer to the
timer port data register depending on the output compare 7 mask register.
14.3.2.5 Timer Count Register (TCNT)
Module Base + 0x0004
15
14
13
12
11
10
9
9
R
W
TCNT15
TCNT14
TCNT13
TCNT12
TCNT11
TCNT10
TCNT9
TCNT8
Reset
0
0
0
0
0
0
0
0
Figure 14-10. Timer Count Register High (TCNTH)
Module Base + 0x0005
7
6
5
4
3
2
1
0
R
TCNT7
W
TCNT6
TCNT5
TCNT4
TCNT3
TCNT2
TCNT1
TCNT0
Reset
0
0
0
0
0
0
0
0
Figure 14-11. Timer Count Register Low (TCNTL)
The 16-bit main timer is an up counter.
A full access for the counter register should take place in one clock cycle. A separate read/write for high
byte and low byte will give a different result than accessing them as a word.
Read: Anytime
S12P-Family Reference Manual, Rev. 1.13
482
Freescale Semiconductor
FREESCALE [ Freescale ]
