Timer Module (TIM16B8CV2) Block Description
TIMCLK (Timer clock)
CLK1
CLK0
4:1 MUX
Clock select
(PAMOD)
Prescaled clock
(PCLK)
Edge detector
PT7
Interrupt
PACNT
MUX
Divide by 64
M clock
Figure 14-2. 16-Bit Pulse Accumulator Block Diagram
16-bit Main Timer
PTn
Edge detector
Set CnF Interrupt
TCn Input Capture Reg.
Figure 14-3. Interrupt Flag Setting
S12P-Family Reference Manual, Rev. 1.13
476
Freescale Semiconductor