128 KByte Flash Module (S12FTMRC128K1V1)
7. Send BDM commands to execute the Program P-Flash command write sequence to program the
Flash security byte to the unsecured state
8. Reset the MCU
13.5.3 Mode and Security Effects on Flash Command Availability
The availability of Flash module commands depends on the MCU operating mode and security state as
shown in Table 13-27.
13.6 Initialization
On each system reset the Flash module executes a reset sequence which establishes initial values for the
Flash Block Configuration Parameters, the FPROT and DFPROT protection registers, and the FOPT and
FSEC registers. The Flash module reverts to using built-in default values that leave the module in a fully
protected and secured state if errors are encountered during execution of the reset sequence. If a double bit
fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set.
CCIF remains clear throughout the reset sequence. The Flash module holds off all CPU access for the
initial portion of the reset sequence. While Flash memory reads and access to most Flash registers are
possible when the hold is removed, writes to the FCCOBIX, FCCOBHI, and FCCOBLO registers are
ignored. Completion of the reset sequence is marked by setting CCIF high which enables writes to the
FCCOBIX, FCCOBHI, and FCCOBLO registers to launch any available Flash command.
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
S12P-Family Reference Manual, Rev. 1.13
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