Chapter 14
Timer Module (TIM16B8CV2) Block Description
Table 14-1. Revision History
Revision
Number
Sections
Affected
Revision Date
Description of Changes
V02.04
1 Jul 2008
14.3.2.12/14- - Revised flag clearing procedure, whereby TEN bit must be set when clearing
488
flags.
14.3.2.13/14-
489
14.3.2.16/14-
492
14.4.2/14-497
14.4.3/14-497
V02.05
9 Jul 2009
14.3.2.12/14- - Revised flag clearing procedure, whereby TEN or PAEN bit must be set
488 when clearing flags.
14.3.2.13/14- - Add fomula to describe prescaler
489
14.3.2.15/14-
491
14.3.2.16/14-
492
14.3.2.19/14-
494
14.4.2/14-497
14.4.3/14-497
V02.06
26 Aug 2009
14.1.2/14-474 - Correct typo: TSCR ->TSCR1
14.3.2.15/14- - Correct reference: Figure 1-25 -> Figure 1-31
491
- Add description, “a counter overflow when TTOV[7] is set”, to be the
14.3.2.2/14-480 condition of channel 7 override event.
14.3.2.3/14-481 - Phrase the description of OC7M to make it more explicit
14.3.2.4/14-482
14.4.3/14-497
14.1 Introduction
The basic timer consists of a 16-bit, software-programmable counter driven by a enhanced programmable
prescaler.
This timer can be used for many purposes, including input waveform measurements while simultaneously
generating an output waveform. Pulse widths can vary from microseconds to many seconds.
This timer contains 8 complete input capture/output compare channels and one pulse accumulator. The
input capture function is used to detect a selected transition edge and record the time. The output compare
function is used for generating output signals or for timer software delays. The 16-bit pulse accumulator
S12P-Family Reference Manual, Rev. 1.13
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