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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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Device Overview MC9S12P-Family  
1.9.1  
Chip Configuration Summary  
The different modes and the security state of the MCU affect the debug features (enabled or disabled).  
The operating mode out of reset is determined by the state of the MODC signal during reset (see Table 1-  
10). The MODC bit in the MODE register shows the current operating mode and provides limited mode  
switching during operation. The state of the MODC signal is latched into this bit on the rising edge of  
RESET.  
Table 1-10. Chip Modes  
Chip Modes  
MODC  
Normal single chip  
Special single chip  
1
0
1.9.1.1  
Normal Single-Chip Mode  
This mode is intended for normal device operation. The opcode from the on-chip memory is being  
executed after reset (requires the reset vector to be programmed correctly). The processor program is  
executed from internal memory.  
1.9.1.2  
Special Single-Chip Mode  
This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The  
background debug module BDM is active in this mode. The CPU executes a monitor program located in  
an on-chip ROM. BDM firmware waits for additional serial commands through the BKGD pin.  
S12P-Family Reference Manual, Rev. 1.13  
Freescale Semiconductor  
43