Device Overview MC9S12P-Family
1.7.4.6
VSSPLL — Ground Pin for PLL
This pin provides ground for the oscillator and the phased-locked loop. The voltage supply of nominally
1.8V is derived from the internal voltage regulator.
1.7.4.7
Power and Ground Connection Summary
Table 1-9. Power and Ground Connection Summary
Nominal
Mnemonic
Description
Voltage
VDDR
5.0 V
External power supply to internal voltage
regulator
VDDX[2:1]
VSSX[2:1]
VDDA
5.0 V
0 V
External power and ground, supply to pin
drivers
5.0 V
0 V
Operating voltage and ground for the
analog-to-digital converters and the
reference for the internal voltage regulator,
allows the supply voltage to the A/D to be
bypassed independently.
VSSA
VRL
VRH
VSS3
0 V
5.0 V
0V
Reference voltages for the analog-to-digital
converter.
Internal power and ground generated by
internal regulator for the internal core.
VSSPLL
0V
Provides operating voltage and ground for
the phased-locked loop. This allows the
supply voltage to the PLL to be bypassed
independently. Internal power and ground
generated by internal regulator.
1.8
System Clock Description
For the system clock description please refer to chapter Chapter 7, “S12 Clock, Reset and Power
Management Unit (S12CPMU).
1.9
Modes of Operation
The MCU can operate in different modes. These are described in 1.9.1 Chip Configuration Summary.
The MCU can operate in different power modes to facilitate power saving when full system performance
is not required. These are described in 1.9.2 Low Power Operation.
Some modules feature a software programmable option to freeze the module status whilst the background
debug module is active to facilitate debugging.
S12P-Family Reference Manual, Rev. 1.13
42
Freescale Semiconductor
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