Serial Peripheral Interface (S12SPIV5)
When the third edge occurs, the value previously latched from the serial data input pin is shifted into the
LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master
data is coupled out of the serial data output pin of the master to the serial input pin on the slave.
1
This process continues for a total of n edges on the SCK line with data being latched on even numbered
edges and shifting taking place on odd numbered edges.
Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and
is transferred to the parallel SPI data register after the last bit is shifted in.
1
After 2n SCK edges:
•
Data that was previously in the SPI data register of the master is now in the data register of the
slave, and data that was in the data register of the slave is in the master.
•
The SPIF flag bit in SPISR is set indicating that the transfer is complete.
Figure 12-14 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or
slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master
and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the
master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or
reconfigured as a general-purpose output not affecting the SPI.
End of Idle State
SCK Edge Number
SCK (CPOL = 0)
Begin
4
End
Begin of Idle State
Transfer
1
2
3
5
6
7
8
9
10 11 12 13 14 15 16
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
MOSI pin
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
tL
t
t
t
L
T
I
MSB first (LSBFE = 0): MSB
LSB first (LSBFE = 1): LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB Minimum 1/2 SCK
for t , t , t
MSB
T
l
L
t = Minimum leading time before the first SCK edge, not required for back-to-back transfers
L
t = Minimum trailing time after the last SCK edge
T
t = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers
I
Figure 12-14. SPI Clock Format 1 (CPHA = 1), with 8-Bit Transfer Width selected (XFRW = 0)
S12P-Family Reference Manual, Rev. 1.13
418
Freescale Semiconductor
FREESCALE [ Freescale ]
