Serial Peripheral Interface (S12SPIV5)
End of Idle State
Begin of Idle State
Begin
3
End
Transfer
1
2
4
5
6
7
8
9
10 11 12 13 14 15 16
SCK Edge Number
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
MOSI pin
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
tL
t
t
t
L
T
I
MSB first (LSBFE = 0): MSB
LSB first (LSBFE = 1): LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB Minimum 1/2 SCK
for t , t , t
MSB
T
l
L
t = Minimum leading time before the first SCK edge
L
t = Minimum trailing time after the last SCK edge
T
t = Minimum idling time between transfers (minimum SS high time)
I
t , t , and t are guaranteed for the master mode and required for the slave mode.
L
T
I
Figure 12-12. SPI Clock Format 0 (CPHA = 0), with 8-bit Transfer Width selected (XFRW = 0)
S12P-Family Reference Manual, Rev. 1.13
416
Freescale Semiconductor
FREESCALE [ Freescale ]
