Serial Peripheral Interface (S12SPIV5)
Table 12-11. Normal Mode and Bidirectional Mode
When SPE = 1
Master Mode MSTR = 1
Slave Mode MSTR = 0
Serial Out
Serial In
MOSI
MISO
MOSI
MISO
Normal Mode
SPC0 = 0
SPI
SPI
Serial Out
Serial In
Serial In
SPI
Serial Out
MOMI
Bidirectional Mode
SPC0 = 1
BIDIROE
SPI
BIDIROE
Serial In
Serial Out
SISO
The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output,
serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift
register.
•
•
•
The SCK is output for the master mode and input for the slave mode.
The SS is the input or output for the master mode, and it is always the input for the slave mode.
The bidirectional mode does not affect SCK and SS functions.
NOTE
In bidirectional master mode, with mode fault enabled, both data pins MISO
and MOSI can be occupied by the SPI, though MOSI is normally used for
transmissions in bidirectional mode and MISO is not used by the SPI. If a
mode fault occurs, the SPI is automatically switched to slave mode. In this
case MISO becomes occupied by the SPI and MOSI is not used. This must
be considered, if the MISO pin is used for another purpose.
12.4.6 Error Conditions
The SPI has one error condition:
•
Mode fault error
12.4.6.1 Mode Fault Error
If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more
than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not
permitted in normal operation, the MODF bit in the SPI status register is set automatically, provided the
MODFEN bit is set.
In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by
the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
421
FREESCALE [ Freescale ]
