Serial Peripheral Interface (S12SPIV5)
As long as no more than one slave device drives the system slave’s serial data output line, it is possible for
several slaves to receive the same transmission from a master, although the master would not receive return
information from all of the receiving slaves.
If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at
the serial data input pin to be latched. Even numbered edges cause the value previously latched from the
serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.
If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to
be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift
into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.
When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA
is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data
1
output pin. After the nth shift, the transfer is considered complete and the received data is transferred into
the SPI data register. To indicate transfer is complete, the SPIF flag in the SPI status register is set.
NOTE
A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or
BIDIROE with SPC0 set in slave mode will corrupt a transmission in
progress and must be avoided.
12.4.3 Transmission Formats
During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially)
simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two
serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that
are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave select
line can be used to indicate multiple-master bus contention.
MASTER SPI
SLAVE SPI
MISO
MOSI
MISO
MOSI
SHIFT REGISTER
SHIFT REGISTER
SCK
SS
SCK
SS
BAUD RATE
GENERATOR
V
DD
Figure 12-11. Master/Slave Transfer Block Diagram
12.4.3.1 Clock Phase and Polarity Controls
Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase
and polarity.
1. n depends on the selected transfer width, please refer to Section 12.3.2.2, “SPI Control Register 2 (SPICR2)
S12P-Family Reference Manual, Rev. 1.13
414
Freescale Semiconductor
FREESCALE [ Freescale ]
