Serial Peripheral Interface (S12SPIV5)
Data A Received
Data B Received
Data C Received
SPIF Serviced
Receive Shift Register
SPIF
Data B
Data A
Data C
Data C
SPI Data Register
Data B
Data A
= Unspecified
= Reception in progress
Figure 12-9. Reception with SPIF serviced in Time
Data A Received
Data B Received
Data C Received
Data B Lost
SPIF Serviced
Receive Shift Register
SPIF
Data B
Data C
Data C
Data A
SPI Data Register
Data A
= Unspecified
= Reception in progress
Figure 12-10. Reception with SPIF serviced too late
12.4 Functional Description
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral
devices. Software can poll the SPI status flags or SPI operation can be interrupt driven.
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set,
the four associated SPI port pins are dedicated to the SPI function as:
•
•
•
•
Slave select (SS)
Serial clock (SCK)
Master out/slave in (MOSI)
Master in/slave out (MISO)
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
411
FREESCALE [ Freescale ]
