Serial Peripheral Interface (S12SPIV5)
SPI
2
2
SPI Control Register 1
BIDIROE
SPI Control Register 2
SPI Status Register
SPC0
CPHA
Slave
Control
CPOL
MOSI
SPIF
MODF SPTEF
Phase +
SCK In
Interrupt Control
Polarity
Control
Slave Baud Rate
Master Baud Rate
SPI
Interrupt
Phase +
Polarity
Control
SCK Out
Request
Port
Control
Logic
SCK
SS
Baud Rate Generator
Counter
Master
Control
Bus Clock
Baud Rate
Prescaler
Clock Select
Shift
Clock
Sample
Clock
SPPR
3
3
SPR
Shifter
LSBFE=0
LSBFE=1
SPI Baud Rate Register
Data In
LSBFE=1
MSB
SPI Data Register
LSB
LSBFE=0
Data Out
LSBFE=0
LSBFE=1
Figure 12-1. SPI Block Diagram
12.2 External Signal Description
This section lists the name and description of all ports including inputs and outputs that do, or may, connect
off chip. The SPI module has a total of four external pins.
12.2.1 MOSI — Master Out/Slave In Pin
This pin is used to transmit data out of the SPI module when it is configured as a master and receive data
when it is configured as slave.
12.2.2 MISO — Master In/Slave Out Pin
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data
when it is configured as master.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
401
FREESCALE [ Freescale ]
