欢迎访问ic37.com |
会员登录 免费注册
发布采购

MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
 浏览型号MC9S12P64CFT的Datasheet PDF文件第190页浏览型号MC9S12P64CFT的Datasheet PDF文件第191页浏览型号MC9S12P64CFT的Datasheet PDF文件第192页浏览型号MC9S12P64CFT的Datasheet PDF文件第193页浏览型号MC9S12P64CFT的Datasheet PDF文件第195页浏览型号MC9S12P64CFT的Datasheet PDF文件第196页浏览型号MC9S12P64CFT的Datasheet PDF文件第197页浏览型号MC9S12P64CFT的Datasheet PDF文件第198页  
S12S Debug Module (S12SDBGV2)  
6.5.10 Scenario 9  
Trigger when a routine/event at A (M2) does not follow either B or C (M1 or M0) before they are executed  
again. This cannot be realized with theS12SDBGV1 SCR encoding due to OR limitations. By changing  
the SCR2 encoding as shown in red this scenario becomes possible.  
Figure 6-39. Scenario 9  
SCR2=1111  
SCR1=0111  
M01  
M01  
M2  
Final State  
State2  
State1  
6.5.11 Scenario 10  
Trigger if an event M0 occurs following up to two successive M2 events without the resetting event M1.  
As shown up to 2 consecutive M2 events are allowed, whereby a reset to State1 is possible after either one  
or two M2 events. If an event M0 occurs following the second M2, before M1 resets to State1 then a trigger  
is generated. Configuring CompA and CompC the same, it is possible to generate a breakpoint on the third  
consecutive occurrence of event M0 without a reset M1.  
Figure 6-40. Scenario 10a  
M1  
SCR2=0100  
SCR3=0010  
SCR1=0010  
M0  
M2  
M2  
Final State  
State3  
State2  
State1  
M1  
Figure 6-41. Scenario 10b  
M0  
SCR2=0011  
SCR3=0000  
SCR1=0010  
M1  
M2  
Final State  
State3  
State2  
State1  
M0  
Scenario 10b shows the case that after M2 then M1 must occur before M0. Starting from a particular point  
in code, event M2 must always be followed by M1 before M0. If after any M2, event M0 occurs before  
M1 then a trigger is generated.  
S12P-Family Reference Manual, Rev. 1.13  
194  
Freescale Semiconductor  
 复制成功!