S12S Debug Module (S12SDBGV2)
Address: 0x0028
7
6
5
4
3
2
1
0
R
W
SZE
0
SZ
TAG
BRK
RW
RWE
NDB
COMPE
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-13. Debug Comparator Control Register DBGACTL (Comparator A)
Address: 0x0028
7
6
5
4
3
2
1
0
R
W
0
SZE
0
SZ
TAG
BRK
RW
RWE
COMPE
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-14. Debug Comparator Control Register DBGBCTL (Comparator B)
Address: 0x0028
7
6
5
4
3
2
1
0
R
W
0
0
0
0
TAG
BRK
RW
RWE
COMPE
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-15. Debug Comparator Control Register DBGCCTL (Comparator C)
Read: DBGACTL if COMRV[1:0] = 00
DBGBCTL if COMRV[1:0] = 01
DBGCCTL if COMRV[1:0] = 10
Write: DBGACTL if COMRV[1:0] = 00 and DBG not armed
DBGBCTL if COMRV[1:0] = 01 and DBG not armed
DBGCCTL if COMRV[1:0] = 10 and DBG not armed
Table 6-22. DBGXCTL Field Descriptions
Field
Description
7
Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the
SZE
associated comparator. This bit is ignored if the TAG bit in the same register is set.
(Comparators 0 Word/Byte access size is not used in comparison
A and B)
1 Word/Byte access size is used in comparison
6
Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the
SZ
associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set.
(Comparators 0 Word access size is compared
A and B) 1 Byte access size is compared
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
169
FREESCALE [ Freescale ]
