S12S Debug Module (S12SDBGV2)
6.3.2.7.1
Debug State Control Register 1 (DBGSCR1)
Address: 0x0027
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
SC3
SC2
SC1
SC0
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-9. Debug State Control Register 1 (DBGSCR1)
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the
targeted next state whilst in State1. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 6-1 and described in 6.3.2.8.1. Comparators must be enabled by setting
the comparator enable bit in the associated DBGXCTL control register.
Table 6-15. DBGSCR1 Field Descriptions
Field
Description
3–0
These bits select the targeted next state whilst in State1, based upon the match event.
SC[3:0]
Table 6-16. State1 Sequencer Next State Selection
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description (Unspecified matches have no effect)
Any match to Final State
Match1 to State3
Match2 to State2
Match1 to State2
Match0 to State2....... Match1 to State3
Match1 to State3.........Match0 to Final State
Match0 to State2....... Match2 to State3
Either Match0 or Match1 to State2
Reserved
Match0 to State3
Reserved
Reserved
Reserved
Either Match0 or Match2 to Final State........Match1 to State2
Reserved
Reserved
The priorities described in Table 6-36 dictate that in the case of simultaneous matches, a match leading to
final state has priority followed by the match on the lower channel number (0,1,2). Thus with
SC[3:0]=1101 a simultaneous match0/match1 transitions to final state.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
165
FREESCALE [ Freescale ]
