S12S Debug Module (S12SDBGV2)
Table 6-22. DBGXCTL Field Descriptions (continued)
Description
Field
5
TAG
Tag Select— This bit controls whether the comparator match has immediate effect, causing an immediate
state sequencer transition or tag the opcode at the matched address. Tagged opcodes trigger only if they
reach the execution stage of the instruction queue.
0 Allow state sequencer transition immediately on match
1 On match, tag the opcode. If the opcode is about to be executed allow a state sequencer transition
4
BRK
Break— This bit controls whether a comparator match terminates a debug session immediately, independent
of state sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled
using the DBGC1 bit DBGBRK.
0 The debug session termination is dependent upon the state sequencer and trigger conditions.
1 A match on this channel terminates the debug session immediately; breakpoints if active are generated,
tracing, if active, is terminated and the module disarmed.
3
RW
Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the
associated comparator. The RW bit is not used if RWE = 0. This bit is ignored if the TAG bit in the same
register is set.
0 Write cycle is matched1Read cycle is matched
2
Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the
associated comparator.This bit is ignored if the TAG bit in the same register is set
0 Read/Write is not used in comparison
RWE
1 Read/Write is used in comparison
1
Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator
NDB
register value or when the data bus differs from the register value. This bit is ignored if the TAG bit in the same
(Comparator A) register is set. This bit is only available for comparator A.
0 Match on data bus equivalence to comparator register contents
1 Match on data bus difference to comparator register contents
0
Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled
COMPE
Table 6-23 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if the
corresponding TAG bit is set since the match occurs based on the tagged opcode reaching the execution
stage of the instruction queue.
Table 6-23. Read or Write Comparison Logic Table
RWE Bit
RW Bit
RW Signal
Comment
RW not used in comparison
RW not used in comparison
Write data bus
0
0
1
1
1
1
x
x
0
0
1
1
0
1
0
1
0
1
No match
No match
Read data bus
S12P-Family Reference Manual, Rev. 1.13
170
Freescale Semiconductor
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