Timer Interface A (TIMA)
I/O Registers
Register Name and Address: TACH1H — $0017
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Indeterminate after reset
TACH1L — $0018
Register Name and Address:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Reset:
Indeterminate after reset
Register Name and Address:
Bit 7
TACH2H — $001A
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Bit 15
Write:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Reset:
Indeterminate after reset
Register Name and Address:
Bit 7
TACH2L — $001B
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Reset:
Indeterminate after reset
Register Name and Address:
Bit 7
TACH3H — $001D
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Bit 15
Write:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Reset:
Indeterminate after reset
Register Name and Address:
Bit 7
TACH3L — $001E
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Reset:
Indeterminate after reset
Figure 16-10. TIMA Channel Registers
(TACH0H/L–TACH3H/L) (Continued)
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA
Data Sheet
253
Timer Interface A (TIMA)
FREESCALE [ Freescale ]
