Timer Interface A (TIMA)
Functional Description
16.3.3 Output Compare
With the output compare function, the TIMA can generate a periodic pulse with a
programmable polarity, duration, and frequency. When the counter reaches the
value in the registers of an output compare channel, the TIMA can set, clear, or
toggle the channel pin. Output compares can generate TIMA CPU interrupt
requests.
16.3.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as
described in 16.3.3 Output Compare. The pulses are unbuffered because
changing the output compare value requires writing the new value over the old
value currently in the TIMA channel registers.
An unsynchronized write to the TIMA channel registers to change an output
compare value could cause incorrect operation for up to two counter overflow
periods. For example, writing a new value before the counter reaches the old value
but after the counter reaches the new value prevents any compare during that
counter overflow period. Also, using a TIMA overflow interrupt routine to write a
new, smaller output compare value may cause the compare to be missed. The
TIMA may pass the new value before it is written.
Use this method to synchronize unbuffered changes in the output compare value
on channel x:
•
When changing to a smaller value, enable channel x output compare
interrupts and write the new value in the output compare interrupt routine.
The output compare interrupt occurs at the end of the current output
compare pulse. The interrupt routine has until the end of the counter
overflow period to write the new value.
•
When changing to a larger output compare value, enable TIMA overflow
interrupts and write the new value in the TIMA overflow interrupt routine. The
TIMA overflow interrupt occurs at the end of the current counter overflow
period. Writing a larger value in an output compare interrupt routine (at the
end of the current pulse) could cause two output compares to occur in the
same counter overflow period.
16.3.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose
output appears on the PTE4/TCH0A pin. The TIMA channel registers of the linked
pair alternately control the output.
Setting the MS0B bit in TIMA channel 0 status and control register (TASC0) links
channel 0 and channel 1. The output compare value in the TIMA channel 0
registers initially controls the output on the PTE4/TCH0A pin. Writing to the TIMA
channel 1 registers enables the TIMA channel 1 registers to synchronously control
the output after the TIMA overflows. At each subsequent overflow, the TIMA
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA Timer Interface A (TIMA)
Data Sheet
239
FREESCALE [ Freescale ]
