Timer Interface A (TIMA)
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: TOF
0
TRST
0
0
R
TIMA Status/Control Register
TOIE
TSTOP
PS2
PS1
PS0
$000E
(TASC) Write:
0
0
See page 245.
TIMA Counter Register High
See page 247.
Reset:
0
Bit 14
R
1
Bit 13
R
0
0
Bit 10
R
0
Bit 9
R
0
Bit 8
R
Read: Bit 15
Bit 12
R
Bit 11
R
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
(TACNTH) Write:
R
0
Reset:
0
0
0
0
0
0
0
Read: Bit 7
Bit 6
R
Bit 5
R
Bit 4
R
Bit 3
R
Bit 2
R
Bit 1
R
Bit 0
R
TIMA Counter Register Low
See page 247.
(TACNTL) Write:
R
0
Reset:
Read:
0
0
0
0
0
0
0
TIMA Counter Modulo
Bit 15
1
14
13
12
11
10
9
1
1
1
Bit 8
1
Register High (TAMODH) Write:
See page 248.
Reset:
1
1
1
1
1
Read:
TIMA Counter Modulo
Register Low (TAMODL) Write:
Bit 7
6
1
5
1
4
1
3
2
Bit 0
1
See page 248.
Reset:
1
1
ELS0B
0
1
ELS0A
0
Read: CH0F
TIMA Channel 0 Status/Control
See page 249.
CH0IE
0
MS0B
0
MS0A
0
TOV0 CH0MAX
Register (TASC0) Write:
0
0
Reset:
Read:
0
9
0
TIMA Channel 0 Register High
Bit 15
14
13
12
11
10
Bit 8
(TACH0H) Write:
See page 252.
Reset:
Read:
Indeterminate after reset
TIMA Channel 0 Register Low
Bit 7
6
5
4
3
2
1
Bit 0
(TACH0L) Write:
See page 252.
Reset:
Read: CH1F
Indeterminate after reset
0
R
0
TIMA Channel 1 Status/Control
See page 249.
CH1IE
MS1A
0
ELS1B
ELS1A
TOV1 CH1MAX
Register (TASC1) Write:
0
0
Reset:
Read:
0
0
0
0
9
0
TIMA Channel 1 Register High
Bit 15
14
13
12
11
10
Bit 8
(TACH1H) Write:
See page 252.
Reset:
Read:
Indeterminate after reset
TIMA Channel 1 Register Low
Bit 7
6
5
4
3
2
1
Bit 0
(TACH1L) Write:
See page 252.
Reset:
Read: CH2F
Indeterminate after reset
TIMA Channel 2 Status/Control
See page 249.
CH2IE
MS2B
0
MS2A
0
ELS2B
0
ELS2A
0
TOV2 CH2MAX
Register (TASC2) Write:
0
0
Reset:
0
0
0
= Reserved
R
Figure 16-3. TIM I/O Register Summary
Data Sheet
236
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA
Timer Interface A (TIMA)
FREESCALE [ Freescale ]
