欢迎访问ic37.com |
会员登录 免费注册
发布采购

MC908MR32CFUE 参数 Datasheet PDF下载

MC908MR32CFUE图片预览
型号: MC908MR32CFUE
PDF下载: 下载PDF文件 查看货源
内容描述: [MC908MR32CFUE ]
分类和应用:
文件页数/大小: 308 页 / 4411 K
品牌: FREESCALE [ Freescale ]
 浏览型号MC908MR32CFUE的Datasheet PDF文件第216页浏览型号MC908MR32CFUE的Datasheet PDF文件第217页浏览型号MC908MR32CFUE的Datasheet PDF文件第218页浏览型号MC908MR32CFUE的Datasheet PDF文件第219页浏览型号MC908MR32CFUE的Datasheet PDF文件第221页浏览型号MC908MR32CFUE的Datasheet PDF文件第222页浏览型号MC908MR32CFUE的Datasheet PDF文件第223页浏览型号MC908MR32CFUE的Datasheet PDF文件第224页  
Serial Peripheral Interface Module (SPI)  
BYTE 1  
BYTE 2  
5
BYTE 3  
7
BYTE 4  
11  
SPI RECEIVE  
COMPLETE  
1
SPRF  
OVRF  
READ  
SPSCR  
2
4
6
9
12  
14  
READ  
SPDR  
3
8
10  
13  
1
2
8
9
BYTE 1 SETS SPRF BIT.  
CPU READS BYTE 2 IN SPDR,  
CLEARING SPRF BIT.  
CPU READS SPSCR WITH SPRF BIT SET  
AND OVRF BIT CLEAR.  
CPU READS SPSCR AGAIN  
TO CHECK OVRF BIT.  
3
4
CPU READS BYTE 1 IN SPDR,  
CLEARING SPRF BIT.  
10  
CPU READS BYTE 2 SPDR,  
CLEARING OVRF BIT.  
CPU READS SPSCR AGAIN  
TO CHECK OVRF BIT.  
11  
12  
13  
BYTE 4 SETS SPRF BIT.  
CPU READS SPSCR.  
5
6
BYTE 2 SETS SPRF BIT.  
CPU READS SPSCR WITH SPRF BIT SET  
AND OVRF BIT CLEAR.  
CPU READS BYTE 4 IN SPDR,  
CLEARING SPRF BIT.  
7
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.  
14  
CPU READS SPSCR AGAIN  
TO CHECK OVRF BIT.  
Figure 15-10. Clearing SPRF When OVRF Interrupt Is Not Enabled  
15.6.2 Mode Fault Error  
Setting the SPMSTR bit selects master mode and configures the SPSCK and  
MOSI pins as outputs and the MISO pin as an input. Clearing SPMSTR selects  
slave mode and configures the SPSCK and MOSI pins as inputs and the MISO pin  
as an output. The mode fault bit, MODF, becomes set any time the state of the  
slave select pin, SS, is inconsistent with the mode selected by SPMSTR.  
To prevent SPI pin contention and damage to the MCU, a mode fault error occurs if:  
The SS pin of a slave SPI goes high during a transmission.  
The SS pin of a master SPI goes low at any time.  
For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be  
set. Clearing the MODFEN bit does not clear the MODF flag but does prevent  
MODF from being set again after MODF is cleared.  
MODF generates a receiver/error CPU interrupt request if the error interrupt enable  
bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same  
CPU interrupt vector. MODF and OVRF can generate a receiver/error CPU  
interrupt request. See Figure 15-11. It is not possible to enable MODF or OVRF  
individually to generate a receiver/error CPU interrupt request. However, leaving  
MODFEN low prevents MODF from being set.  
Data Sheet  
220  
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0  
Serial Peripheral Interface Module (SPI)  
MOTOROLA  
 复制成功!