Serial Peripheral Interface Module (SPI)
Error Conditions
an overflow error always indicates the loss of data. Clear the overflow flag by
reading the SPI status and control register and then reading the SPI data register.
OVRF generates a receiver/error CPU interrupt request if the error interrupt enable
bit (ERRIE) is also set. MODF and OVRF can generate a receiver/error CPU
interrupt request. See Figure 15-11. It is not possible to enable MODF or OVRF
individually to generate a receiver/error CPU interrupt request. However, leaving
MODFEN low prevents MODF from being set.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an
overflow condition. Figure 15-9 shows how it is possible to miss an overflow. The
first part of Figure 15-9 shows how it is possible to read the SPSCR and SPDR to
clear the SPRF without problems. However, as illustrated by the second
transmission example, the OVRF bit can be set in between the time that SPSCR
and SPDR
are read.
BYTE 1
1
BYTE 2
4
BYTE 3
6
BYTE 4
8
SPRF
OVRF
READ
SPSCR
2
5
5
READ
SPDR
3
7
1
2
BYTE 1 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
6
7
3
4
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
BYTE 2 SETS SPRF BIT.
8
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.
Figure 15-9. Missed Read of Overflow Condition
In this case, an overflow can easily be missed. Since no more SPRF interrupts can
be generated until this OVRF is serviced, it is not obvious that bytes are being lost
as more transmissions are completed. To prevent this, either enable the OVRF
interrupt or do another read of the SPSCR following the read of the SPDR. This
ensures that the OVRF was not set before the SPRF was cleared and that future
transmissions can set the SPRF bit. Figure 15-10 illustrates this process.
Generally, to avoid this second SPSCR read, enable the OVRF interrupt to the
CPU by setting the ERRIE bit.
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA Serial Peripheral Interface Module (SPI)
Data Sheet
219
FREESCALE [ Freescale ]
