External Interrupt (IRQ)
8.4 IRQ Pin
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector
fetch, software clear, or reset clears the IRQ latch.
If the MODE1 bit is set, the IRQ pin is both falling-edge-sensitive and low-level-
sensitive. With MODE1 set, both of these actions must occur to clear the IRQ1
latch:
•
Vector fetch, software clear, or reset — A vector fetch generates an interrupt
acknowledge signal to clear the latch. Software can generate the interrupt
acknowledge signal by writing a logic 1 to the ACK1 bit in the interrupt status
and control register (ISCR). The ACK1 bit is useful in applications that poll
the IRQ pin and require software to clear the IRQ1 latch. Writing to the ACK1
bit can also prevent spurious interrupts due to noise. Setting ACK1 does not
affect subsequent transitions on the IRQ pin. A falling edge that occurs after
writing to the ACK1 bit latches another interrupt request. If the IRQ1 mask
bit, IMASK1, is clear, the CPU loads the program counter with the vector
address at locations $FFFA and $FFFB.
•
Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic 0, the
IRQ1 latch remains set.
8.5 IRQ Pin
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector
fetch, software clear, or reset clears the IRQ latch.
If the MODE1 bit is set, the IRQ pin is both falling-edge-sensitive and low-level-
sensitive. With MODE1 set, both of these actions must occur to clear the IRQ1
latch:
•
Vector fetch, software clear, or reset — A vector fetch generates an interrupt
acknowledge signal to clear the latch. Software can generate the interrupt
acknowledge signal by writing a logic 1 to the ACK1 bit in the interrupt status
and control register (ISCR). The ACK1 bit is useful in applications that poll
the IRQ pin and require software to clear the IRQ1 latch. Writing to the ACK1
bit can also prevent spurious interrupts due to noise. Setting ACK1 does not
affect subsequent transitions on the IRQ pin. A falling edge that occurs after
writing to the ACK1 bit latches another interrupt request. If the IRQ1 mask
bit, IMASK1, is clear, the CPU loads the program counter with the vector
address at locations $FFFA and $FFFB.
•
Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic 0, the
IRQ1 latch remains set.
The vector fetch or software clear and the return of the IRQ pin to logic 1 can occur
in any order. The interrupt request remains pending as long as the IRQ pin is at
logic 0.
Data Sheet
104
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
External Interrupt (IRQ)
MOTOROLA
FREESCALE [ Freescale ]
