External Interrupt (IRQ)
Interrupt signals on the IRQ pin are latched into the IRQ1 latch. An interrupt latch
remains set until one of the following actions occurs:
•
Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the latch that caused the vector fetch.
•
Software clear — Software can clear an interrupt latch by writing to the
appropriate acknowledge bit in the interrupt status and control register
(ISCR). Writing a logic 1 to the ACK1 bit clears the IRQ1 latch.
•
Reset — A reset automatically clears both interrupt latches.
The external interrupt pins are falling-edge-triggered and are software-configurable
to be both falling-edge and low-level-triggered. The MODE1 bit in the ISCR
controls the triggering sensitivity of the IRQ pin.
When the interrupt pin is edge-triggered only, the interrupt latch remains set until a
vector fetch, software clear, or reset occurs.
When the interrupt pin is both falling-edge and low-level-triggered, the interrupt
latch remains set until both of these occur:
•
•
Vector fetch, software clear, or reset
Return of the interrupt pin to logic 1
The vector fetch or software clear can occur before or after the interrupt pin returns
to logic 1. As long as the pin is low, the interrupt request remains pending.
When set, the IMASK1 bit in the ISCR masks all external interrupt requests. A
latched interrupt request is not presented to the interrupt priority logic unless the
IMASK bit is clear.
NOTE:
The interrupt mask (I) in the condition code register (CCR) masks all interrupt
requests, including external interrupt requests. (See Figure 8-3.)
Data Sheet
102
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
External Interrupt (IRQ)
MOTOROLA
FREESCALE [ Freescale ]
