Chapter 21
Break Module (BRK)
21.1 Introduction
This section describes the break module. The break module can generate a break interrupt that stops
normal program flow at a defined address to enter a background program.
21.2 Features
Features of the break module include:
•
•
•
•
Accessible input/output (I/O) registers during the break interrupt
CPU-generated break interrupts
Software-generated break interrupts
COP disabling during break interrupts
Addr.
Register Name
Bit 7
6
5
4
3
2
1
SBSW
Note
0
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
R
R
R
R
R
R
R
SIM Break Status Register
(SBSR)
$FE00
SIM Break Flag Control
Register
(SBFCR)
BCFE
0
R
R
R
R
R
R
R
$FE03
$FE0C
$FE0D
$FE0E
Break Address
Register High
(BRKH)
Bit 15
0
14
13
0
12
0
11
0
10
0
9
0
1
Bit 8
0
0
Break Address
Register Low
(BRKL)
Bit 7
0
6
5
4
3
2
Bit 0
0
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
Break Status and Control
Register
(BRKSCR)
BRKE
0
0
0
0
0
0
0
Note: Writing a logic 0 clears BW.
= Unimplemented
= Reserved
R
Figure 21-1. Break Module I/O Register Summary
21.3 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors
to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
291
FREESCALE [ Freescale ]
