Break Module (BRK)
21.5.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint
address. Reset clears the break address registers.
Address: $FE0C
Bit 7
Bit 15
0
6
14
0
5
13
0
4
12
0
3
11
0
2
10
0
1
9
0
Bit 0
Bit 8
0
Read:
Write:
Reset:
Figure 21-4. Break Address Register High (BRKH)
Address: $FE0D
Bit 7
6
6
0
5
5
0
4
4
0
3
3
0
2
2
0
1
1
0
Bit 0
Bit 0
0
Read:
Bit 7
Write:
Reset:
0
Figure 21-5. Break Address Register Low (BRKL)
21.5.3 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait
mode. The flag is useful in applications requiring a return to wait mode after exiting from a break interrupt.
Address:
$FE00
Bit 7
6
5
4
3
2
1
SBSW
Note
0
Bit 0
R
Read:
Write:
Reset:
R
R
R
R
R
R
Note: Writing a logic 0 clears SBSW.
R
= Reserved
Figure 21-6. SIM Break Status Register (SBSR)
SBSW — Break Wait Bit
This status bit is set when a break interrupt causes an exit from wait mode or stop mode. Clear SBSW
by writing a logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break interrupt routine. The user can modify the return address on the stack
by subtracting 1 from it. The following code is an example.
MC68HC908AP Family Data Sheet, Rev. 4
294
Freescale Semiconductor
FREESCALE [ Freescale ]
