Break Module (BRK)
The following events can cause a break interrupt to occur:
•
A CPU-generated address (the address in the program counter) matches the contents of the break
address registers.
•
Software writes a logic 1 to the BRKA bit in the break status and control register.
When a CPU-generated address matches the contents of the break address registers, the break interrupt
begins after the CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the
break routine ends the break interrupt and returns the MCU to normal operation. Figure 21-2 shows the
structure of the break module.
IAB15–IAB8
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
IAB15–IAB0
CONTROL
BREAK
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
IAB7–IAB0
Figure 21-2. Break Module Block Diagram
21.3.1 Flag Protection During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during
the break state.
21.3.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
•
•
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC and $FFFD
($FEFC and $FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
21.3.3 TIMI and TIM2 During Break Interrupts
A break interrupt stops the timer counters.
21.3.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V
is present on the RST pin.
TST
21.4 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
MC68HC908AP Family Data Sheet, Rev. 4
292
Freescale Semiconductor
FREESCALE [ Freescale ]
