Chapter 20
Low-Voltage Inhibit (LVI)
20.1 Introduction
This section describes the low-voltage inhibit (LVI) module. The LVI module monitors the voltage on the
V
pin and V
pin, and can force a reset when V voltage falls below V
, or V voltage falls
DD
REG
DD
TRIPF1
REG
below V
.
TRIPF2
NOTE
The V
pin is the output of the internal voltage regulator and is
REG
guaranteed to meet operating specification as long as V is within the
DD
MCU operating voltage.
The LVI feature is intended to provide the safe shutdown of the
microcontroller and thus protection of related circuitry prior to any
application V voltage collapsing completely to an unsafe level. It is not
DD
intended that users operate the microcontroller at lower than the specified
operating voltage, VDD.
20.2 Features
Features of the LVI module include:
•
•
•
•
Independent voltage monitoring circuits for V and V
DD REG
Independent disable for V and V
LVI circuits
DD
REG
Programmable LVI reset
Programmable stop mode operation
Addr.
Register Name
Bit 7
Read: LVIOUT
Write:
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
LVI Status Register
(LVISR)
$FE0F
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 20-1. LVI I/O Register Summary
20.3 Functional Description
Figure 20-2 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module
contains independent bandgap reference circuit and comparator for monitoring the V voltage and the
DD
V
voltage. An LVI reset performs a MCU internal reset and drives the RST pin low to provide
REG
low-voltage protection to external peripheral devices.
LVISTOP, LVIPWRD, LVIRSTD, and LVIREGD are in the CONFIG1 register. See Chapter 3
Configuration & Mask Option Registers (CONFIG & MOR) for details of the LVI configuration bits. Once
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
287
FREESCALE [ Freescale ]
