LVI Status Register
20.3.4 Forced Reset Operation
In applications that require V to remain above the V
level, enabling LVI resets allows the LVI
DD
TRIPF1
module to reset the MCU when V falls below the V
level. In the CONFIG1 register, the LVIPWRD
DD
TRIPF1
and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets.
20.3.5 Voltage Hysteresis Protection
Once the LVI has triggered (by having V fall below V
), the LVI will maintain a reset condition until
TRIPF1
DD
V
rises above the rising trip point voltage, V
. This prevents a condition in which the MCU is
DD
TRIPR1
continually entering and exiting reset if V is approximately equal to V
. V
is greater than
DD
TRIPF1
TRIPR1
V
by the hysteresis voltage, V
.
TRIPF1
HYS
20.4 LVI Status Register
The LVI status register (LVISR) indicates if the V voltage was detected below V
or V
voltage
REG
DD
TRIPF1
was detected below V
.
TRIPF2
Address:
$FE0F
Bit 7
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
Read: LVIOUT
Write:
0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 20-3. LVI Status Register
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V or V
falls below their respective trip voltages. Reset
REG
DD
clears the LVIOUT bit.
Table 20-1. LVIOUT Bit Indication
VDD, VREG
LVIOUT
VDD > VTRIPR1
and
0
VREG > VTRIPR2
VDD < VTRIPF1
or
1
VDD < VTRIPF2
VTRIPF1 < VDD < VTRIPR1
or
Previous value
VTRIPF2 < VREG< VTRIPR2
20.5 LVI Interrupts
The LVI module does not generate interrupt requests.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
289
FREESCALE [ Freescale ]
