Low-Voltage Inhibit (LVI)
an LVI reset occurs, the MCU remains in reset until V rises above V
and V
rises above
DD
TRIPR1
REG
V
, which causes the MCU to exit reset. The output of the comparator controls the state of the
TRIPR2
LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
V
DD
STOP INSTRUCTION
LVISTOP
FROM CONFIG1
LVIPWRD
FROM CONFIG1
LVIRSTD
FROM CONFIG1
V
V
> V
≤ V
= 0
= 1
LOW V
DD
DD
TRIPR1
TRIPF1
DD
DETECTOR
LVI RESET
V
V
> V
= 0
= 1
REG
REG
TRIPR2
TRIPF2
LOW V
REG
DETECTOR
≤ V
LVIOUT
TO LVISR
FROM CONFIG1
LVIREGD
FROM CONFIG1
LVISTOP
STOP INSTRUCTION
V
REG
Figure 20-2. LVI Module Block Diagram
20.3.1 Low V Detector
DD
The low V detector circuit monitors the V voltage and forces a LVI reset when the V voltage falls
DD
DD
DD
below the trip voltage, V
. The V LVI circuit can be disabled by the setting the LVIPWRD bit in
TRIPF1
DD
CONFIG1 register.
20.3.2 Low V
Detector
REG
The low V
detector circuit monitors the V
voltage and forces a LVI reset when the V
voltage
REG
REG
REG
falls below the trip voltage, V
. The V
LVI circuit can be disabled by the setting the LVIREGD bit
TRIPF2
REG
in CONFIG1 register.
20.3.3 Polled LVI Operation
In applications that can operate at V levels below the V
level, software can monitor V by polling
DD
DD
TRIPF1
the LVIOUT bit. In the CONFIG1 register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
MC68HC908AP Family Data Sheet, Rev. 4
288
Freescale Semiconductor
FREESCALE [ Freescale ]
