COP Control Register
19.3.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the CONFIG1 register.
Address:
$001F
Bit 7
6
5
4
3
2
SSREC
0
1
STOP
0
Bit 0
COPD
0
Read:
Write:
Reset:
COPRS
0
LVISTOP LVIRSTD LVIPWRD LVIREGD
0
0
0
0
Figure 19-2. Configuration Register 1 (CONFIG1)
COPRS — COP Rate Select Bit
COPRS selects the COP time out period. Reset clears COPRS.
13
4
1 = COP time out period = 2 – 2 ICLK cycles
18
4
0 = COP time out period = 2 – 2 ICLK cycles
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
19.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address:
$FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Low byte of reset vector
Clear COP counter
Unaffected by reset
Figure 19-3. COP Control Register (COPCTL)
19.5 Interrupts
The COP does not generate CPU interrupt requests.
19.6 Monitor Mode
When monitor mode is entered with V
on the IRQ1 pin, the COP is disabled as long as V
remains
TST
TST
on the IRQ1 pin or the RST pin. When monitor mode is entered by having blank reset vectors and not
having V on the IRQ1 pin, the COP is automatically disabled until a POR occurs.
TST
19.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
285
FREESCALE [ Freescale ]
