Chapter 19
Computer Operating Properly (COP)
19.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if
allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset
by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the
configuration register 1 (CONFIG1).
19.2 Functional Description
Figure 19-1 shows the structure of the COP module.
RESET CIRCUIT
12-BIT COP PRESCALER
ICLK
RESET STATUS REGISTER
STOP INSTRUCTION
INTERNAL RESET SOURCES
RESET VECTOR FETCH
COPCTL WRITE
COP CLOCK
6-BIT COP COUNTER
COPEN (FROM SIM)
COP DISABLE
(COPD FROM CONFIG1)
RESET
CLEAR
COPCTL WRITE
COP COUNTER
COP RATE SEL
(COPRS FROM CONFIG1)
Figure 19-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by
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software, the COP counter overflows and generates an asynchronous reset after 2 – 2 or 2 – 2
ICLK cycles, depending on the state of the COP rate select bit, COPRS, in the CONFIG1 register. With
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a 2 – 2 ICLK cycle overflow option, a 88-kHz ICLK gives a COP timeout period of ~93ms. Writing any
value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter
and stages 12 through 5 of the prescaler.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
283
FREESCALE [ Freescale ]
