Functional Description
INTERNAL
DATA BUS
READ DDRAx
WRITE DDRAx
DISABLE
DDRAx
PTAx
RESET
WRITE PTAx
READ PTAx
PTAx/ADCx
ADC0–ADC7
(8 CHANNELS)
DISABLE
ADC DATA REGISTERS
ADRH0 ADRL0
ADRL1
ADRL2
VREFH
VREFL
ADRL3
ADC
VOLTAGE IN
CONVERSION
COMPLETE
(V
)
ADIN
CHANNEL
SELECT
INTERRUPT
LOGIC
10-BIT ADC
ADCICLK
AIEN
COCO
MUX
ASCAN
CGMXCLK
CLOCK
GENERATOR
BUS CLOCK
ADCH[4:0]
ADIV[2:0] ADICLK
2-BIT UP-COUNTER
AUTO[1:0]
Figure 15-2. ADC Block Diagram
15.3.3 Conversion Time
Conversion starts after a write to the ADSCR. One conversion will take between 16 and 17 ADC clock
cycles, therefore:
16 to17 ADC cycles
Conversion time =
ADC frequency
Number of bus cycles = conversion time × bus frequency
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
249
FREESCALE [ Freescale ]
