Multi-Master IIC Interface (MMIIC)
14.7.1 Data Sequence
(a) Master Transmit Mode
TX Data1
START
Address
0
ACK
ACK
TX DataN
ACK
STOP
MMTXBE=0
MMRW=0
MMAST=1
Data1 → MMDTR
MMTXBE=1
MMTXIF=1
Data2 → MMDTR
MMTXBE=1
MMTXIF=1
Data3 → MMDTR
MMNAKIF=1
MMAST=0
MMTXBE=0
MMTXBE=1
MMTXIF=1
DataN+2 → MMDTR
(b) Master Receive Mode
RX Data1
START
Address
1
ACK
ACK
RX DataN
NAK
STOP
MMRXBF=0
MMRW=1
MMAST=1
MMTXBE=0
MMNAKIF=1
MMAST=0
Data1 → MMDRR
MMRXIF=1
MMRXBF=1
DataN → MMDRR
MMRXIF=1
MMRXBF=1
(dummy data → MMDTR)
(c) Slave Transmit Mode
TX Data1
START
Address
1
ACK
ACK
TX DataN
NAK
STOP
MMTXBE=1
MMRXBF=0
MMRXIF=1
MMNAKIF=1
MMTXBE=0
MMTXBE=1
MMTXIF=1
Data2 → MMDTR
MMTXBE=1
MMTXIF=1
MMRXBF=1
MMATCH=1
MMSRW=1
DataN+2 → MMDTR
Data1 → MMDTR
(d) Slave Receive Mode
RX Data1
START
Address
0
ACK
ACK
RX DataN
ACK
STOP
Data1 → MMDRR
MMRXIF=1
MMRXBF=1
DataN → MMDRR
MMRXIF=1
MMRXBF=1
MMTXBE=0
MMRXBF=0
MMRXIF=1
MMRXBF=1
MMATCH=1
MMSRW=0
Shaded data packets indicate transmissions by the MCU
Figure 14-12. Data Transfer Sequences for Master/Slave Transmit/Receive Modes
MC68HC908AP Family Data Sheet, Rev. 4
242
Freescale Semiconductor
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