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MC908AP32CFAE 参数 Datasheet PDF下载

MC908AP32CFAE图片预览
型号: MC908AP32CFAE
PDF下载: 下载PDF文件 查看货源
内容描述: [MC908AP32CFAE]
分类和应用:
文件页数/大小: 325 页 / 4102 K
品牌: FREESCALE [ Freescale ]
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Multi-Master IIC Interface (MMIIC)  
14.3 I/O Pins  
The MMIIC module uses two I/O pins, shared with standard port I/O pins. The full name of the MMIIC I/O  
pins are listed in Table 14-1. The generic pin name appear in the text that follows.  
The SDA and SDL pins are open-drain. When configured as general purpose output pins (PTB0 and  
PTB1), pullup resistors must be connected to these pins.  
Table 14-1. Pin Name Conventions  
MMIIC Generic Pin Names:  
Full MCU Pin Names:  
PTB0/SDA  
Pin Selected for MMIIC Function By:  
SDA  
SCL  
MMEN bit in MMCR1 ($0049)  
PTB1/SCL  
Addr.  
Register Name  
Bit 7  
MMAD7  
1
6
MMAD6  
0
5
4
3
MMAD3  
0
2
MMAD2  
0
1
Bit 0  
Read:  
Write:  
Reset:  
Read:  
Write:  
Reset:  
MMAD5  
MMAD4  
MMAD1 MMEXTAD  
MMIIC Address Register  
(MMADR)  
$0048  
$0049  
$004A  
$004B  
$004C  
$004D  
$004E  
$004F  
1
0
0
0
0
0
0
MMCLRBB  
0
MMCRCBYTE  
MMEN  
0
MMIEN  
0
MMTXAK REPSEN  
MMIIC Control Register 1  
(MMCR1)  
0
MMAST  
0
0
MMRW  
0
0
0
0
0
0
Read: MMALIF MMNAKIF  
MMBB  
MMCRCEF  
Unaffected  
MMIIC Control Register 2  
(MMCR2)  
Write:  
0
0
0
0
Reset:  
0
0
0
Read: MMRXIF  
MMTXIF MMATCH MMSRW MMRXAK MMCRCBF MMTXBE MMRXBF  
0
MMIIC Status Register  
(MMSR)  
Write:  
Reset:  
Read:  
0
0
0
0
0
1
0
1
0
MMIIC Data Transmit  
MMTD7  
0
MMTD6  
MMTD5  
MMTD4  
MMTD3  
MMTD2  
MMTD1  
MMTD0  
Register Write:  
(MMDTR)  
Reset:  
0
0
0
0
0
0
0
Read: MMRD7  
MMRD6  
MMRD5  
MMRD4  
MMRD3  
MMRD2  
MMRD1  
MMRD0  
MMIIC Data Receive  
Register Write:  
(MDDRR)  
Reset:  
0
0
0
0
0
0
0
0
Read: MMCRCD7 MMCRCD6 MMCRCD5 MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCD0  
Write:  
MMIIC CRC Data Register  
(MMCRDR)  
Reset:  
Read:  
0
0
0
0
0
0
0
0
0
0
0
MMBR2  
1
0
MMBR1  
0
0
MMBR0  
0
MMIIC Frequency Divider  
Register Write:  
(MMFDR)  
Reset:  
0
0
0
0
0
= Unimplemented  
Figure 14-1. MMIIC I/O Register Summary  
14.4 Multi-Master IIC System Configuration  
The multi-master IIC system uses a serial data line SDA and a serial clock line SCL for data transfer. All  
devices connected to it must have open collector (drain) outputs and the logical-AND function is  
performed on both lines by two pull-up resistors.  
MC68HC908AP Family Data Sheet, Rev. 4  
230  
Freescale Semiconductor  
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