Chapter 14
Multi-Master IIC Interface (MMIIC)
14.1 Introduction
The multi-master IIC (MMIIC) interface is a two wire, bidirectional serial bus which provides a simple,
efficient way for data exchange between devices. The interface is designed for internal serial
communication between the MCU and other IIC devices. It has hardware generated START and STOP
signals; and byte by byte interrupt driven software algorithm.
This bus is suitable for applications which need frequent communications over a short distance between
a number of devices. It also provides a flexibility that allows additional devices to be connected to the bus.
The maximum data rate is 100k-bps, and the maximum communication distance and number of devices
that can be connected is limited by a maximum bus capacitance of 400pF.
This MMIIC interface is also SMBus (System Management Bus) version 1.0 and 1.1 compatible, with
hardware cyclic redundancy code (CRC) generation, making it suitable for smart battery applications.
14.2 Features
Features of the MMIC module include:
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Full SMBus version 1.0/1.1 compliance
Multi-master IIC bus standard
Software programmable for one of eight different serial clock frequencies
Software controllable acknowledge bit generation
Interrupt driven byte by byte data transfer
Calling address identification interrupt
Arbitration loss detection and no-ACK awareness in master mode and automatic mode switching
from master to slave
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Auto detection of R/W bit and switching of transmit or receive mode accordingly
Detection of START, repeated START, and STOP signals
Auto generation of START and STOP condition in master mode
Repeated start generation
Master clock generator with eight selectable baud rates
Automatic recognition of the received acknowledge bit
Busy detection
Software enabled 8-bit CRC generation/decoding
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
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FREESCALE [ Freescale ]
