System Design Information
8.6 Substrate Capacitors for the MPC7455, 483 CBGA
Figure 23 shows the connectivity of the substrate capacitor pads for the MPC7455, 483 CBGA. All capacitors are
100 nF.
A1 Corner
Pad Number
Capacitor
C7-1
C7-2
C8-1
C8-2
C9-1
C9-2
-1
-2
C1
C2
OV
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DD
V
DD
C3
OV
DD
DD
C4
OV
C5
V
DD
C6
OV
DD
DD
C7
AV
C8
OV
GV
GV
DD
DD
DD
C9
C10
C11
C12
C3-2
C3-1
C2-2
C2-1
C1-2
C1-1
V
DD
GV
DD
Figure 23. Substrate Bypass Capacitors for the MPC7455, 483 CBGA
9 System Design Information
This section provides system and thermal design recommendations for successful application of the MPC7455.
9.1 PLL Configuration
The MPC7455 PLL is configured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus) frequency, the PLL
configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the
MPC7455 is shown in Table 17 for a set of example frequencies. In this example, shaded cells represent settings
that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with the 1-GHz
column in Table 8. Note that these configurations were different in devices prior to Rev F; see Section 11.2, “Part
Numbers Not Fully Addressed by This Document,” for more information regarding documentation of prior
revisions.
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
Freescale Semiconductor
45
FREESCALE [ Freescale ]
