System Design Information
10 Ω
V
AV
DD
DD
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 24. PLL Power Supply Filter Circuit
9.3 Decoupling Recommendations
Due to the MPC7455 dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC7455 can generate transient power surges and high frequency noise in its power supply,
especially while driving large capacitive loads. This noise must be prevented from reaching other components in the
MPC7455 system, and the MPC7455 itself requires a clean, tightly regulated source of power. Therefore, it is
recommended that the system designer place at least one decoupling capacitor at each V , OV , and GV pin
DD
DD
DD
of the MPC7455. It is also recommended that these decoupling capacitors receive their power from separate V
,
DD
OV /GV , and GND power planes in the PCB, utilizing short traces to minimize inductance.
DD
DD
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic surface mount technology (SMT) capacitors
should be used to minimize lead inductance, preferably 0508 or 0603 orientations where connections are made along
the length of the part. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design:
A Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous recommendations for decoupling
Freescale microprocessors, multiple small capacitors of equal value are recommended over using multiple values of
capacitance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the
V
, GV , and OV planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors
DD
DD DD
should have a low equivalent series resistance (ESR) rating to ensure the quick response time necessary. They should
also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk
capacitors: 100–330 µF (AVX TPS tantalum or Sanyo OSCON).
9.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level.
Unused active low inputs should be tied to OV . Unused active high inputs should be connected to GND. All NC
DD
(no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V , OV , GV , and GND pins in the MPC7455.
DD
DD
DD
If the L3 interface is not used, GV
connected to BVSEL.
should be connected to the OV power plane, and L3VSEL should be
DD
DD
9.5 Output Buffer DC Impedance
The MPC7455 processor bus and L3 I/O drivers are characterized over process, voltage, and temperature. To
measure Z , an external resistor is connected from the chip pad to OV or GND. Then, the value of each resistor
0
DD
is varied until the pad voltage is OV /2 (see Figure 25).
DD
The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When
data is held low, SW2 is closed (SW1 is open), and R is trimmed until the voltage at the pad equals OV /2. R
N
DD
N
then becomes the resistance of the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
Freescale Semiconductor
49
FREESCALE [ Freescale ]
