Electrical and Thermal Characteristics
Table 12 provides the L3 bus interface AC timing specifications for the configuration as shown in Figure 9,
assuming the timing relationships shown in Figure 10 and the loading shown in Figure 8.
Table 12. L3 Bus Interface AC Timing Specifications for MSUG2
At recommended operating conditions. See Table 4.
8
All Speed Grades
Parameter
Symbol
Unit Notes
L3OH0 = 0, L3OH1 = 0 L3OH0 = 0, L3OH1 =1 L3OH0 = 1, L3OH1 = 0 L3OH0 = 1, L3OH1 = 1
Min
Max
Min
Max
Min
Max
Min
Max
L3_CLK rise
and fall time
tL3CR
tL3CF
,
—
1.0
—
1.0
—
1.0
—
1.0
ns
ns
1
Setup times: tL3DVEH
Data and
parity
,
– 0.1
—
—
– 0.1
—
—
– 0.1
—
—
– 0.1
—
—
2, 3,
4
tL3DVEL
Input hold
times: Data
and parity
tL3DXEH
tL3DXEL
,
tL3_CLK/4
+ 0.30
tL3_CLK/4
+ 0.30
tL3_CLK/4
+ 0.30
tL3_CLK/4
+ 0.30
ns
2, 4
Valid times:
Data and
parity
tL3CHDV
tL3CLDV
,
—
—
(–tL3_CLK/4)
+ 0.60
—
—
(– tL3_CLK/4)
+ 0.40
—
—
(– tL3_CLK/4)
+ 0.20
—
—
(– tL3_CLK/4) ns
+ 0.00
5, 6,
7
Valid times:
All other
outputs
tL3CHOV
tL3_CLK/4
+ 0.80
tL3_CLK/4
+ 0.60
tL3_CLK/4
+ 0.40
tL3_CLK/4
+ 0.20
ns
ns
ns
ns
5, 7
Output hold
times: Data
and parity
tL3CHDX
,
tL3_CLK/4
– 0.40
—
—
tL3_CLK/4
– 0.60
—
—
tL3_CLK/4
– 0.80
—
—
tL3_CLK/4
– 1.00
—
—
5, 6,
7
tL3CLDX,
Output hold
times: All
other outputs
tL3CHOX tL3_CLK/4
– 0.20
tL3_CLK/4
– 0.40
tL3_CLK/4
– 0.60
tL3_CLK/4
– 0.80
5, 7
L3_CLK to
high
tL3CLDZ
—
tL3_CLK/2
—
tL3_CLK/2
—
tL3_CLK/2
—
tL3_CLK/2
impedance:
Data and
parity
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
Freescale Semiconductor
23
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