Freescale Semiconductor, Inc.
Ele c tric a l Sp e c ific a tions
SS
INPUT
13
12
12
3
1
SCK (CPOL = 0)
(INPUT
151
4
4
5
2
SCK (CPOL = 1)
INPUT
13
SLAVE LSB OUT
11
9
8
MISO
INPUT
SLAVE MSB OUT
BITS 6–1
BITS 6–1
NOTE
6
7
10
MOSI
OUTPUT
MSB IN
LSB IN
Note: Not defined, but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS
INPUT
13
12
1
SCK (CPOL = 0)
INPUT
5
4
4
5
2
3
SCK (CPOL = 1)
INPUT
10
SLAVE MSB OUT
12
10
13
9
8
MISO
OUTPUT
NOTE
BITS 6–1
BITS 6–1
SLAVE LSB OUT
6
7
11
MOSI
INPUT
MSB IN
LSB IN
Note: Not defined, but normally LSB of character previously transmitted
b) SPI Slave Timing (CPHA = 1)
Figure 13-9. SPI Slave Timing
Technical Data
190
MC68HC705C8A — Rev. 3
Electrical Specifications
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