Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Multiple-SPI Systems
Example:
LDA #$1C ; MSTR = 1, CPOL = 1, CPHA = 1,
; SPR1 = SPR0 = 0
STA SPCR ; SPI control register
LDA #$4C ; MSTR = 0, SPE = 1, CPOL = 1, CPHA = 1,
; SPR1 = SPR0 = 0
STA SPCR ; SPI control register
11.5 Multiple-SPI Systems
In a multiple-SPI system, all PD4/SCK pins are connected together, all
PD3/MOSI pins are connected together, and all PD2/MISO pins are
connected together.
Before a transmission, one SPI is configured as master and the rest are
configured as slaves. Figure 11-4 is a block diagram showing a single
master SPI and three slave SPIs.
MASTER MCU
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
V
DD
2
I/O
PORT
1
0
SLAVE MCU 2
SLAVE MCU 1
SLAVE MCU 0
Figure 11-4. One Master and Three Slaves Block Diagram
Figure 11-5 is another block diagram with two master/slave SPIs and
three slave SPIs.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Serial Peripheral Interface (SPI)
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