Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Addr.
Register Name
Bit 7
SPIE
0
6
5
4
3
CPOL
U
2
CPHA
U
1
SPR1
U
Bit 0
SPR0
U
Read:
SPI Control Register
SPE
MSTR
$000A
(SPCR) Write:
See page 149.
Reset:
0
0
Read: SPIF
WCOL
MODF
SPI Status Register
(SPSR) Write:
$000B
$000C
See page 151.
Reset:
Read:
0
0
0
SPI Data Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
BIt 2
Bit 1
Bit 0
(SPDR) Write:
See page 149.
Reset:
Unaffected by reset
= Unimplemented U = Unaffected
Figure 11-2. SPI I/O Register Summary
11.4 Operation
The master/slave SPI allows full-duplex, synchronous, serial
communication between the microcontroller unit (MCU) and peripheral
devices, including other MCUs. As the 8-bit shift register of a master SPI
transmits each byte to another device, a byte from the receiving device
enters the master SPI shift register. A clock signal from the master SPI
synchronizes data transmission.
Only a master SPI can initiate transmissions. Software begins the
transmission from a master SPI by writing to the SPI data register
(SPDR). The SPDR does not buffer data being transmitted from the SPI.
Data written to the SPDR goes directly into the shift register and begins
the transmission immediately under the control of the serial clock. The
transmission ends after eight cycles of the serial clock when the SPI flag
(SPIF) becomes set. At the same time that SPIF becomes set, the data
shifted into the master SPI from the receiving device transfers to the
SPDR. The SPDR buffers data being received by the SPI. Before the
master SPI sends the next byte, software must clear the SPIF bit by
reading the SPSR and then accessing the SPDR.
Technical Data
142
MC68HC705C8A — Rev. 3
Serial Peripheral Interface (SPI)
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