Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Operation
In a slave SPI, data enters the shift register under the control of the serial
clock from the master SPI. After a byte enters the shift register of a slave
SPI, it transfers to the SPDR. To prevent an overrun condition, slave
software must then read the byte in the SPDR before another byte enters
the shift register and is ready to transfer to the SPDR.
Figure 11-3 shows how a master SPI exchanges data with a slave SPI.
PD3/MOSI
SPI SHIFT REGISTER
SPI SHIFT REGISTER
PD2/MISO
PD5/SS
7
6
5
4
3
2
1
0
7 6 5 4 3 2 1 0
SPDR ($000C)
SPDR ($000C)
PD4/SCK
MASTER MCU
SLAVE MCU
Figure 11-3. Master/Slave Connections
11.4.1 Pin Functions in Master Mode
Setting the MSTR bit in the SPI control register (SPCR) configures the
SPI for operation in master mode. The master-mode functions of the SPI
pins are:
• PD4/SCK (serial clock) — In master mode, the PD4/SCK pin is the
synchronizing clock output.
• PD3/MOSI (master output, slave input) — In master mode, the
PD3/MOSI pin is the serial output.
• PD2/MISO (master input, slave output) — In master mode, the
PD2/MISO pin is configured as the serial input.
• PD5/SS (slave select) — In master mode, the PD5/SS pin protects
against driver contention caused by the simultaneous operation of
two SPIs in master mode. A logic 0 on the PD5/SS pin of a master
SPI disables the SPI, clears the MSTR bit, and sets the mode-fault
flag (MODF).
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Serial Peripheral Interface (SPI)
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