Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
SPI I/O Registers
11.9.1 SPI Data Register
The SPDR shown in Figure 11-7 is the read buffer for characters
received by the SPI. Writing a byte to the SPDR places the byte directly
into the SPI shift register.
Address: $000C
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Unaffected by reset
Figure 11-7. SPI Data Register (SPDR)
11.9.2 SPI Control Register
• Enables SPI interrupt requests
• Enables the SPI
• Configures the SPI as master or slave
• Selects serial clock polarity, phase, and frequency
Address: $000A
Bit 7
SPIE
0
6
SPE
0
5
4
MSTR
0
3
CPOL
U
2
CPHA
U
1
SPR1
U
Bit 0
SPR0
U
Read:
Write:
Reset:
= Unimplemented
U = Unaffected
Figure 11-8. SPI Control Register (SPCR)
SPIE — SPI Interrupt Enable Bit
This read/write bit enables SPI interrupts. Reset clears the SPIE bit.
1 = SPI interrupts enabled
0 = SPI interrupts disabled
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Serial Peripheral Interface (SPI)
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