Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
– CPHA = 1 — A slave SPI can cause a write collision error by
writing to the SPDR while receiving a transmission, that is,
between the first active SCK edge and the end of the eighth
SCK cycle. The error does not affect the transmission from the
master SPI, but the byte that caused the error is lost.
11.7.3 Overrun Error
Failing to read the byte in the SPDR before a subsequent byte enters the
shift register causes an overrun condition. In an overrun condition, all
incoming data is lost until software clears SPIF. The overrun condition
has no flag.
11.8 SPI Interrupts
The SPIF bit in the SPSR indicates a byte has shifted into or out of the
SPDR. The SPIF bit is a source of SPI interrupt requests. The SPI
interrupt enable bit (SPIE) in the SPCR is the local mask for SPIF
interrupts.
The MODF bit in the SPSR indicates a mode error and is a source of SPI
interrupt requests. The MODF bit is set when a logic 0 occurs on the
PD5/SS pin while the MSTR bit is set. The SPI interrupt enable bit (SPIE)
in the SPCR is the local mask for MODF interrupts.
11.9 SPI I/O Registers
These input/output (I/O) registers control and monitor SPI operation:
• SPI data register (SPDR)
• SPI control register (SPCR)
• SPI status register (SPSR)
Technical Data
148
MC68HC705C8A — Rev. 3
Serial Peripheral Interface (SPI)
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