Freescale Semiconductor, Inc.
FLASH-1 Memory
FLASH Program/Margin Read Operation
ordinary read mode except that a built-in counter stretches the data
access for an additional eight cycles to allow sensing of the lower cell
current. Margin read mode imposes a more stringent read condition on
the bitcell to ensure the bitcell is programmed with enough margin for
long-term data retention. During these eight cycles, the COP counter
continues to run. The user must account for these extra cycles within
COP feed loops. A margin read cycle can only follow a page
programming operation.
To program and margin read the FLASH memory, use this step-by-step
algorithm. See 24.13 Memory Characteristics for a detailed description
of the times used in this algorithm.
1. Set the PGM bit. This configures the memory for program
operation and enables the latching of address and data for
programming.
2. Read from the block protect register (FLBPR1).
3. Write data to the eight bytes of the page being programmed. This
requires eight separate write operations.
4. Set the HVEN bit.
5. Wait for a time, tPROG
6. Clear the HVEN bit.
.
7. Wait for a time, tHVTV
.
8. Set the MARGIN bit.
9. Wait for a time, tVTP
10. Clear the PGM bit.
.
11. Wait for a time, tHVD
.
12. Read back data in margin read mode. This is done in eight
separate read operations which are each stretched by eight
cycles.
13. Clear the MARGIN bit.
NOTE: While these operations must be performed in the order shown, other
unrelated operations may occur between the steps.
MC68HC908AS60 — Rev. 1.0
Technical Data
FLASH-1 Memory
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