Freescale Semiconductor, Inc.
FLASH-1 Memory
FLASH Charge Pump Frequency Control
4.5 FLASH Charge Pump Frequency Control
The internal charge pump, required for program, margin read, and erase
operations, is designed to operate most efficiently with a 2-MHz clock.
The charge pump clock is derived from the bus clock. Table 4-1 shows
how the FDIV bits are used to select a charge pump frequency based on
the bus clock frequency. Program, margin read, and erase operations
cannot be performed if the bus clock frequency is below 2 MHz.
Table 4-1. Charge Pump Clock Frequency
FDIV1
FDIV0
Pump Clock Frequency
Bus frequency ÷ 1
Bus frequency ÷ 2
Bus frequency ÷ 2
Bus frequency ÷ 4
Bus Clock Frequency
1.8–2.5 MHz
0
0
1
1
0
1
0
1
3.6–5.0 MHz
3.6–5.0 MHz
7.2–8.4 MHz
4.6 FLASH Erase Operation
See 24.13 Memory Characteristics for a detailed description of the
times used in this algorithm. Use this step-by-step procedure to erase a
block of FLASH memory:
1. Set the ERASE, BLK0, BLK1, FDIV0, and FDIV1 bits in the
FLASH-1 control register. See Table 4-2 for block sizes and
Table 4-1 for FDIV settings.
2. Ensure target portion of array is unprotected by reading the block
protect register, FLBPR1: address $FF80. See 4.8 FLASH Block
Protection and 4.8.1 FLASH-1 Block Protect Register for more
information.
3. Write to any FLASH address with any data within the block
address range desired.
4. Set the HVEN bit.
5. Wait for a time, tErase
.
6. Clear the HVEN bit.
MC68HC908AS60 — Rev. 1.0
Technical Data
FLASH-1 Memory
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